The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Mobile computing devices such as cellular phones, MP3 players, global positioning system (GPS) devices, etc. are typically powered using both line power and battery power. The mobile computing devices typically include a processor, memory and a display, which consume power during operation. The processor generally executes both simple applications that are less processing-intensive and complex applications that are more processing-intensive. Therefore, the capabilities of the processor such as processing speed are typically selected to match the performance requirements of the most processing-intensive applications that will be executed.
One significant limitation of mobile computing devices relates to the amount of time for which the devices can be operated using batteries without recharging. Using a high-speed processor that meets the performance requirements of the processing-intensive applications generally increases power consumption, which corresponds to a relatively short battery life.
Referring now to FIGS. 1A and 1B, some desktop and laptop computers use multiple processor integrated circuits (ICs) or a single processor IC with multiple cores. These systems can be of different types. As used herein, the term processor is used to refer to an IC with one or more processing cores. A multi-core processor refers to an IC, a system-on-chip (SOC), or a system-in-package (SIP) with two or more processing cores.
In FIG. 1A, an asymmetric multi-processor (MP) system 1 comprising a main processor 2 and one or more secondary processors 3 is shown. The asymmetric MP system 1 may also be implemented as a single IC or SOC with a main core and a secondary core. The main processor 2 has a different instruction set architecture (ISA) than the secondary processors 3. An operating system (OS) may run on the main processor 2. Applications may run on the secondary processors 3. The secondary processors 3 do not run threads of the OS and may be invisible to an OS scheduler. An OS driver interface to a real-time OS (RTOS) may run on the secondary processors 3. Key functions may be offloaded to the secondary processors 3 for power saving and reducing the duty cycle of the main processor 2. For example only, the asymmetric MP system 1 can be used for special-purpose processing (e.g., video, 3D graphics, etc.). Since the secondary processors 3 may run in addition to the main processor 2 when applications are executed, the asymmetric MP system 1 may consume large amounts of power.
In FIG. 1B, a symmetric MP system 5 may comprise N identical processors, where N is an integer greater than 1. The symmetric MP system 5 may also be implemented as a single IC or SOC with N identical cores. N may be proportional to the processing load of the symmetric MP system 5. The N processors use the same ISA. The N processors may be visible to the OS scheduler. The N processors may have transparent access to system resources including memory and input/output (I/O). Depending on the processing load, one or more of the N processors can be utilized to execute applications. The high cost and high power consumption of the symmetric MP system 5 tends to make this architecture unsuitable for lower cost mobile devices.